檔案狀態:    住戶編號:1165213
 向天 天晴 的日記本
快速選單
到我的日記本
看他的最新日記
加入我的收藏
瀏覽我的收藏
明天放無心假 《前一篇 回他的日記本 後一篇》 向晴的生日
 切換閱讀模式  回應  給他日記貼紙   給他愛的鼓勵  檢舉
篇名: Floorplan
作者: 向天 天晴 日期: 2009.02.27  天氣:  心情:

我最近的工作


Floorplan (microelectronics)


From Wikipedia, the free encyclopedia


Jump to: navigation, search






Mock floorplan in an IC layout editor window



In electronic design automation, a floorplan of an integrated circuit is a schematic representaion of tentative placement of its major functional blocks.


In modern electronic design process floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to chip design.


Depending on the design methodology, the actual notions of floorplan may differ.



[edit] Mathematical models and optimization problems related to floorplans


In some approaches floorplan may be a partition of the whole chip area into axis aligned rectangles to be occupied by IC blocks. This partition is subject to various constraints and requirements of optimization: block area, aspect ratios, estimated total measure of interconnects, etc.


Finding good floorplans has been a research area in combinatorial optimization. Most of problems related to finding optimal floorplans are NP-hard, i.e., require vast computational resources. Therefore the most common approach is to use various optimization heuristics for finding good solutions.


Another approach is to restrict design methodology to certain classes of floorplans, such as sliceable floorplans, see below.


 


 


Floorplanning is the act of designing of a floorplan, which is a kind of bird's-eye view of a structure.



[edit] Electronic design automation


In electronic design automation, floorplanning takes in some of the geometrical limitations in a design. Examples of this are:



  • bonding pads for contacting off-chip (often using wire bonding) are normally located at the circumference of the chip;

  • line drivers often have to be located as close to bonding pads as possible;

  • chip area is therefore in some cases given a minimum area in order to fit in the required number of pads;

  • areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and arithmetic logic unit;

  • purchased intellectual property blocks (such as a processor core) come in ready defined area blocks;

  • some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.

標籤:
瀏覽次數:395    人氣指數:3195    累積鼓勵:140
 切換閱讀模式  回應  給他日記貼紙   給他愛的鼓勵 檢舉
給本文愛的鼓勵:  最新愛的鼓勵
明天放無心假 《前一篇 回他的日記本 後一篇》 向晴的生日
 
住戶回應
 
時間:2009-08-26 21:11
她, 48歲,亞洲其他,其他
*給你留了一則留言*
  
 
時間:2009-08-26 20:04
她, 48歲,亞洲其他,其他
*給你留了一則留言*
  
作者回覆說[2009-08-26 20:26]:

哦,這是我的專業啊:p

 
時間:2009-02-28 01:07
她, 39歲,亞洲其他,出版
*給你留了一則留言*
  
作者回覆說[2009-02-28 07:44]:

都不是
我是Project Leader
所以我要先弄一個初版的
問過所有人的意見之後
他們覺得沒問題
他們會處理細節
簡單的說
就是打雜的,這個Project所有的事
都跟我相關,甚至別人故意兩手一攤,不決定事情
說PL決定(後面的意思就是,你這個PL負決定之後成敗之責)



給我們一個讚!